`timescale 1ns / 1ps
/*--------------------------------------------------------------------*\
FileName        : updater.v
Author          ：hpy
Email           ：yuan_hp@qq.com
Date            ：2025年06月06日
Description     ：
\*--------------------------------------------------------------------*/
`ifndef __updater_v__
`define __updater_v__
`include "uart_rx.v"
module updater #(
    parameter clk_freq = 12000000 ,
    parameter baud  = 9600 
)(
    input clk,
    input rst_n,

    input wire rx , 

    output o_led,

    output wire       o_updating , 
    output reg [11:0] o_mem_addr ,
    output reg [17:0] o_mem_dat ,
    output reg        o_mem_we  

);

/* ------------------ function -------------------- */

/* -------------------- param --------------------- */

/*---------------------- reg ---------------------- */
reg [55:0] read_buf ;
/*----------------------- wire ---------------------*/
wire  rx_ready;
wire [7:0] rx_data;
/*--------------------- assign ---------------------*/
assign o_updating = ~(&read_buf) ;
/*---------------------- blk -----------------------*/

always @(posedge clk) begin
	if( ~rst_n) begin 
        read_buf <= {56{1'b1}};
        o_mem_we <= 1'b0;
	end else begin
        o_mem_we <= 1'b0;
        //接收到数据 解析数据 
        if(rx_ready) begin 
            read_buf <= {read_buf[47:0] , rx_data} ;
            //写 RAM 指令 
            if(read_buf[47:40]==8'h00 && rx_data == 8'hff ) begin
                o_mem_addr <= read_buf[35:24] ;
                o_mem_dat  <= read_buf[17:0]  ;
                o_mem_we <= 1'b1 ;
            end
        end 
	end
end 

assign o_led = rx_ready ;


uart_rx #(clk_freq, baud) urx (
	.clk(clk),
	.rx(rx),
	.rx_ready(rx_ready),
	.rx_data(rx_data)
);


endmodule

`endif 